sig_gen

class caf_verilog.sig_gen.SigGen(freq_res, fs, n_bits, output_dir='.')[source]

Bases: CafVerilogBase

gen_tb(freq=None)[source]

Generate a testbench for the specified frequency.

Parameters:

freq –

Returns:

params_dict() → dict[source]
template_dict(inst_name=None)[source]
write_lut_values()[source]
Returns:

Return type:

None

write_module()[source]
write_sig_gen_tb_module(freq=None)[source]

Write out a testbench file to test the sig_gen module.

Parameters:

freq –

Returns:

caf_verilog.sig_gen.calc_smallest_phase_size(f_clk, freq_res, n_bits) → int[source]
caf_verilog.sig_gen.freq_step_str(phase_bits, increment)[source]
caf_verilog.sig_gen.lut_values(n_bits)[source]

Create and return an array of values quantized to the number of bits requested. The list is always 2 ** (n_bits + 1) in length for n_bits.

Parameters:

n_bits –

Returns:

Return type:

list

caf_verilog.sig_gen.phase_bits(f_clk, freq_res) → int[source]

Calculate the number of bits the phase accumulator will need.

Parameters:

  • f_clk – Sampling rate/clock frequency

  • freq_res – Frequency resolution required

Returns:

caf_verilog.sig_gen.phase_increment(f_out, phase_bits, f_clk) → int[source]

Calculate the phase increment required to produce the desired frequency.

Parameters:

  • f_out –

  • phase_bits –

  • f_clk –

Returns: