caf

class caf_verilog.caf.CAF(reference, received, foas, ref_i_bits=12, ref_q_bits=0, rec_i_bits=12, rec_q_bits=0, fs=625000.0, n_bits=8, pipeline=True, output_dir='.')[source]

Bases: CafVerilogBase

freq_res()[source]
gen_submodules()[source]
gen_tb()[source]
params_dict() → dict[source]
phase_increment_values() → list[source]
template_dict(inst_name=None)[source]
write_module()[source]
write_phase_increment_values()[source]
write_tb_module()[source]
async caf_verilog.caf.retrieve_max(caf: CAF, dut, cycle_timeout=20)[source]
async caf_verilog.caf.send_input_data(caf: CAF, dut, cycle_timeout=10)[source]
Parameters:

  • caf – CAF instance to retrieve module values

  • dut – cocotb design under test

  • cycle_timeout – Number of clock cycles to wait for ready signal

async caf_verilog.caf.set_increment_values(caf: CAF, dut)[source]
Parameters:

  • caf – CAF instance to retrieve module values

  • dut – cocotb design under test

caf_verilog.caf.simple_caf(x, y, foas, fs)[source]

Produce values for a surface plot of the Complex Ambiguity Function. The return is the CAF surface and a time delay range normalized by the sampling frequency.

Parameters:

  • x – Use x as a reference signal.

  • y – Use y as a captured signal.

  • foas – Frequency offsets, provided as a list/iterable object.

  • fs – Sampling frequency

Returns:

caf_res, dt